S1165 Datasheet, PDF (12/23 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION LOW DROPOUT

HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR
S-1165 Series
Rev.4.1_00
 Operation
1. Basic operation
Figure 11 shows the block diagram of the S-1165 Series.
The error amplifier compares the reference voltage (V_ref) with feedback voltage (V_fb), which is the output
voltage resistance-divided by feedback resistors (R_s and R_f). It supplies the gate voltage necessary to
maintain the constant output voltage which is not influenced by the input voltage and temperature
change, to the output transistor.
VIN
Current
supply
V_ref
Error
amplifier
−
+
Reference voltage
circuit
*1
R_f
V_fb
R_s
VOUT
VSS
*1. Parasitic diode
Figure 11
2. Output transistor
In the S-1165 Series, a low on-resistance P-channel MOS FET is used as the output transistor.
Be sure that V_OUT does not exceed V_IN + 0.3 V to prevent the voltage regulator from being damaged due
to reverse current flowing from the VOUT pin through a parasitic diode to the VIN pin, when the potential
of V_OUT became higher than V_IN.
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Seiko Instruments Inc.