S93L76A Datasheet, PDF (10/37 Pages) Seiko Instruments Inc – LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM

LOW VOLTAGE OPERATION 3-WIRE SERIAL E²PROM
S-93L76A
Rev.6.0_02
 Initial Delivery State
Initial delivery state of all addresses is “FFFFh”.
 Operation
All instructions are executed by making CS “H” and then inputting DI at the rising edge of the SK pulse. An instruction
is input in the order of its start bit, instruction, address, and data. The start bit is recognized when “H” of DI is input at
the rising edge of SK after CS has been made “H”. As long as DI remains “L”, therefore, the start bit is not recognized
even if the SK pulse is input after CS has been made “H”. The SK clock input while DI is “L” before the start bit is input
is called a dummy clock. By inserting as many dummy clocks as required before the start bit, the number of clocks the
internal serial interface of the CPU can send out and the number of clocks necessary for operation of the serial memory
IC can be adjusted. Inputting the instruction is complete when CS is made “L”. CS must be made “L” once during the
period of tCDS in between instructions.
“L” of CS indicates a standby status. In this status, input of SK and DI is invalid, and no instruction is accepted.
1. Reading (READ)
The READ instruction is used to read the data at a specified address. When this instruction is executed, the
address A0 is input at the rising edge of SK and the DO pin, which has been in a high-impedance (High-Z) state,
outputs “L”. Subsequently, 16 bits of data are sequentially output at the rising edge of SK.
If SK is output after the 16-bit data of the specified address has been output, the address is automatically
incremented, and the 16-bit data of the next address is then output. By inputting SK sequentially with CS kept at
“H”, the data of the entire memory space can be read. When the address is incremented from the last address (A8
… A1 A0 = 1 … 1 1), it returns to the first address (A8 … A1 A0 = 0 … 0 0).
CS
SK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 26 27 28 29 30 31 32 42 43 44 45 46 47 48
DI
1 1 0 X A₈ A₇ A₆ A₅ A₄ A₃ A₂ A₁ A₀
High-Z
DO
0 D₁₅ D₁₄ D₁₃
D₂ D₁ D₀ D₁₅ D₁₄ D₁₃
D₂ D₁ D₀ D₁₅ D₁₄ D₁₃
A₈A₇A₆A₅A₄A₃A₂A₁A₀+1
A₈A₇A₆A₅A₄A₃A₂A₁A₀+2
Figure 6 Read Timing
High-Z
10