HYS64-72V2200GU-8 Datasheet, PDF (9/17 Pages) Siemens Semiconductor Group – 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module

HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
Parameter
Symbol
Limit Values
Unit
-8
PC100
2-2-2
-8-3
PC100
3-2-3
-10
PC66
2-2-2
min. max. min. max. min. max.
Refresh Cycle
Self Refresh Exit Time
t_SREX
Refresh Period (4096 cycles) t_REF
10 – 10 – 10 – ns
64 – 64 – 64 – ms
Note
9)
8)
Read Cycle
Data Out Hold Time
t_OH
Data Out to Low Impedance t_LZ
Time
Data Out to High Impedance t_HZ
Time
DQM Data Out Disable
t_DQZ
Latency
3
–
3
–
3
– ns 4)
0
–
0
–
0
– ns
3
9
3
9
3
9 ns 10)
2
–
2
–
2
– CLK
Write Cycle
Data input to Precharge (write t_DPL
recovery)
Data In to Active/refresh
t_DAL
DQM Write Mask Latency
t_DQW
2
–
2
–
2
– CLK
5
–
5
–
5
– CLK 11)
0
–
0
–
0
– CLK
Semiconductor Group
9