HYM64V2005GU-50 Datasheet, PDF (9/14 Pages) Siemens Semiconductor Group – 3.3V 2M x 64-Bit EDO-DRAM Module 3.3V 2M x 72-Bit EDO-DRAM Module

HYM 64(72)V2005GU-50/-60
2M x 64/72 DRAM Module
AC Characteristics ⁵⁾⁶⁾
T_A = 0 to 70 °C,V_CC = 3.3 V ± 0.3 V, t_T = 2 ns
Parameter
Symbol
Limit Values
Unit
-50
-60
min. max. min. max.
common parameters
Random read or write cycle time
RAS precharge time
RAS pulse width
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay
RAS hold time
CAS hold time
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
t_RC
84
t_RP
30
t_RAS
50
t_CAS
8
t_ASR
0
t_RAH
8
t_ASC
0
t_CAH
8
t_RCD
12
t_RAD
10
t_RSH
13
t_CSH
40
t_CRP
5
t_T
1
t_REF
–
–
104 –
ns
–
40
–
ns
10k 60
10k ns
10k 10
10k ns
–
0
–
ns
–
10
–
ns
–
0
–
ns
–
10
–
ns
37
14
45
ns
25
12
30
ns
15
–
ns
50
–
ns
–
5
–
ns
50
1
50
ns
32
–
32
ms
16E
Note
7
Read Cycle
Access time from RAS
t_RAC
–
50
–
60
ns
8, 9
Access time from CAS
t_CAC
–
13
–
15
ns
8, 9
Access time from column address
t_AA
–
25
–
30
ns
8,10
OE access time
t_OEA
–
13
–
15
ns
Column address to RAS lead time
t_RAL
25
–
30
–
ns
Read command setup time
t_RCS
0
–
0
–
ns
Read command hold time
t_RCH
0
–
0
–
ns
11
Read command hold time referenced to t_RRH
0
–
0
–
ns
11
RAS
CAS to output in low-Z
Output buffer turn-off delay
Output turn-off delay from OE
t_CLZ
0
t_OFF
0
t_OEZ
0
–
0
13
0
13
0
–
ns
8
15
ns
12
15
ns
12
Semiconductor Group
9