HYS64V4120GU Datasheet, PDF (8/11 Pages) Siemens Semiconductor Group – 3.3V 4M x 64-Bit 2 BANK SDRAM Module 3.3V 4M x 72-Bit 2 BANK SDRAM Module

HYS64(72)V4120GU-10
4M x 64/72 SDRAM-Module
Parameter
CAS to CAS delay time (same bank)
Symbol
Limit Values
-10
min
max
t_CCD
1
–
Unit Note
CLK
Refresh Cycle
Self Refresh Exit Time
Refresh Period (4096 cycles)
t_SREX
t_REF
2Clk
+t_RC
–
–
ns 8
64
ms 7
Read Cycle
Data Out Hold Time
t_OH
Data Out to Low Impedance Time
t_LZ
Data Out to High Impedance Time
t_HZ
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
3
–
ns
0
–
ns
9
–
6
ns
–
8
ns
–
25
ns
DQM Data Out Disable Latency
t_DQZ
2
–
CLK
Write Cycle
Data In Setup Time
Data In Hold Time
Data input to Precharge
Data In to Active/refresh
DQM Write Mask Latency
t_DS
3
t_DH
1
t_DPL
2
t_DAL
5
t_DQW
0
–
ns
–
ns
–
CLK
–
CLK 10
–
CLK
Semiconductor Group
8