HYS64V4120GU Datasheet, PDF (10/11 Pages) Siemens Semiconductor Group – 3.3V 4M x 64-Bit 2 BANK SDRAM Module 3.3V 4M x 72-Bit 2 BANK SDRAM Module

HYS64(72)V4120GU-10
4M x 64/72 SDRAM-Module
A serial presence detect storage device - E ²PROM - is assembled onto the module. Information about the module
configuration, speed, etc. is written into the E ²PROM device during module production using a serial presence
detect protocol ( I²C synchronous 2-wire bus)
PD-Table:
Byte#
Description
0 Number of SPD bytes
1 Total bytes in Serial PD
2 Memory Type
3 Number of Row Addresses (without BS bits)
4 Number of Column Addresses
(for x8 SDRAM)
5 Number of DIMM Banks
6 Module Data Width
7 Module Data Width (contd’ )
8 Module Interface Levels
9 SDRAM Cycle Time at CL=3
10 SDRAM Access Time from Clock at CL=3
11 Dimm Config (Error Det/Corr.)
12 Refresh Rate/Type
13 SDRAM width, Primary
14 Error Checking SDRAM data width
15 Minimum clock delay for back-to-back ran-
dom column address
16 Burst Length supported
17 Number of SDRAM banks
18 Supported CAS Latencies
19 CS Latencies
20 WE Latencies
21 SDRAM DIMM module attributes
22 SDRAM Device Attributes :General
23 SDRAM Cycle Time at CL = 2
24 SDRAM Access Time from Clock at CL = 2
25 SDRAM Cylce Time at CL = 1
26 SDRAM Access Time from Clock at CL = 1
27 Minimum Row Precharge Time
28 Minimum Row Active to Row Active delay
tRRD
SPD Entry Value
128
256
SDRAM
11
9
2
64 / 72
0
LVTTL
10.0 ns
8.0 ns
none / ECC
Self-Refresh,
15.6µs
x8
n/a / x8
t_ccd = 1 CLK
1, 2, 4, 8 & full page
2
CAS latency = 1, 2
&3
CS latency = 0
Write latency = 0
non buffered/non
reg.
Vcc tol +/- 10%
15.0 ns
9.0 ns
30 ns
27 ns
30 ns
20 ns
Hex
x64 x72
-10 -10
80 80
08 08
04 04
0B 0B
09 09
02 02
40 48
00 00
01 01
A0 A0
80 80
00 02
80 80
08 08
00 08
01 01
8F 8F
02 02
07 07
01 01
01 01
00 00
06 06
F0 F0
90 90
78 78
6C 6C
1E 1E
14 14
Semiconductor Group
10