HYM72V8025GS-50- Datasheet, PDF (6/11 Pages) Siemens Semiconductor Group – 8M x 72-Bit EDO- DRAM Module

HYM72V8025/35GS-50/-60
8M x 72-ECC EDO-Module
Parameter
Symbol
Average V_CC supply current during RAS
I_CC3
only refresh cycles:
-50 version
-60 version
Limit Values
min.
max.
–
1260
–
1080
(RAS cycling, CAS = V_IH , t_RC = t_RC min.)
Average V_CC supply current during hyper I_CC4
page mode (EDO):
-50 version
–
945
-60 version
–
765
(RAS = V_IL, CAS, address cycling
t_PC = t_PC min.)
Standby V_CC supply current
I_CC5
–
(RAS = CAS = V_CC – 0.2 V,
one address change within 15,6 µs trc)
Average V_CC supply current during
I_CC6
CAS-before-RAS refresh mode:
-50 version
–
-60 version
–
30
1260
1080
(RAS, CAS cycling, t_RC = t_RC min.)
Unit Test
Condition
2) 4)
mA
mA
mA ^{2) 3) 4)}
mA
mA –
mA ^{2) 4)}
mA
Capacitance
T_A = 0 to 70 °C; V_CC = 3.3 V ± 0.3 V; f = 1 MHz
Parameter
Input capacitance (A0 to A11,B0)
Input capacitance (RAS0, RAS2)
Input capacitance (CAS0, CAS4)
Input capacitance (WE0,WE2,OE0,OE2)
I/O capacitance (DQ0-DQ71)
Symbol
C_I1
C_I2
C_I3
C_I4
C_IO1
Limit Values
min.
max.
–
10
–
50
–
15
–
15
–
15
Unit
pF
pF
pF
pF
pF
Semiconductor Group
6