C515C Datasheet, PDF (53/69 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

C515C
– Slow-down mode
The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by 32. This slows down all parts of the controller, the CPU and all
peripherals, to 1/32-th of their normal operating frequency. Slowing down the frequency
significantly reduces power consumption. The slow down mode can be combined with the idle
mode.
Table 10 gives a general overview of the entry and exit conditions of the power saving modes.
Table 10
Power Saving Modes Overview
Mode
Idle mode
Entering
(2-Instruction
Example
ORL PCON, #01H
ORL PCON, #20H
Software
ORL PCON, #02H
Power-Down Mode ORL PCON, #40H
Hardware
HWPD = low
Power-Down Mode
Slow Down Mode ORL PCON,#10H
Leaving by
Ocurrence of an
interrupt from a
peripheral unit
Hardware Reset
Hardware Reset
Short low pulse at
pin P3.2/INT0
HWPD = high
ANL PCON,#0EFH
or
Hardware Reset
Remarks
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock
Oscillator is stopped;
contents of on-chip RAM and
SFR’s are maintained;
C515C is put into its reset state
and the oscillator is stopped;
ports become floating outputs
Oscillator frequency is reduced
to 1/32 of its nominal frequency
In the power down mode of operation, V_CC can be reduced to minimize power consumption. It must
be ensured, however, that V_CC is not reduced before the power down mode is invoked, and that V_CC
is restored to its normal operating level, before the power down mode is terminated.
If e.g. the idle mode is left through an interrupt, the microcontroller state (CPU, ports, peripherals)
remains preserved. If a power saving mode is left by a hardware reset, the microcontroller state is
disturbed and replaced by the reset state of the C515C.
Semiconductor Group
53
1997-07-01