C515C Datasheet, PDF (17/69 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

C515C
Control of XRAM/CAN Controller Access
The XRAM in the C515C is a memory area that is logically located at the upper end of the external
memory space, but is integrated on the chip. Because the XRAM and the CAN controller is used in
the same way as external data memory the same instruction types (MOVX) must be used for
accessing the XRAM. Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to the
XRAM and the CAN controller.
Special Function Register SYSCON (Address B1H)
Reset Value : X010XX01B
Bit No. MSB
7
6
5
4
3
B1H
– PMOD EALE RMAP –
LSB
2
1
0
– XMAP1 XMAP0 SYSCON
The function of the shaded bits is not described in this section.
Bit
XMAP1
XMAP0
Function
XRAM/CAN controller visible access control
Control bit for RD/WR signals during XRAM/CAN Controller accesses. If
addresses are outside the XRAM/CAN controller address range or if
XRAM is disabled, this bit has no effect.
XMAP1 = 0 : The signals RD and WR are not activated during accesses to
the XRAM/CAN Controller
XMAP1 = 1 : Ports 0, 2 and the signals RD and WR are activated during
accesses to XRAM/CAN Controller. In this mode, address
and data information during XRAM/CAN Controller accesses
are visible externally.
Global XRAM/CAN controller access enable/disable control
XMAP0 = 0 : The access to XRAM and CAN controller is enabled.
XMAP0 = 1 : The access to XRAM and CAN controller is disabled (default
after reset). All MOVX accesses are performed via the
external bus. Further, this bit is hardware protected.
Bit XMAP0 is hardware protected. If it is reset once (XRAM/CAN controller access enabled) it
cannot be set by software. Only a reset operation will set the XMAP0 bit again.
The XRAM/CAN controller can be accessed by read/write instructions (MOVX A,DPTR, MOVX
@DPTR,A), which use the 16-bit DPTR for indirect addressing. For accessing the XRAM or CAN
controller, the effective address stored in DPTR must be in the range of F700H to FFFFH.
The XRAM can be also accessed by read/write instructions (MOVX A,@Ri, MOVX @Ri,A), which
use only an 8-bit address (indirect addressing with registers R0 or R1). Therefore, a special page
register XPAGE which provides the upper address information (A8-A15) during 8-bit XRAM
accesses. The behaviour of Port 0 and P2 during a MOVX access depends on the control bits
XMAP0 and XMAP1 in register SYSCON and on the state of pin EA. Table 2 lists the various
operating conditions.
Semiconductor Group
17
1997-07-01