C515C Datasheet, PDF (50/69 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

C515C
Fail Save Mechanisms
The C515C offers two on-chip peripherals which monitor the program flow and ensure an automatic
"fail-safe" reaction for cases where the controller’s hardware fails or the software hangs up:
– A programmable watchdog timer (WDT) with variable time-out period from 512 microseconds
up to approx. 1.1 seconds at 6 MHz.
– An oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the
microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for
a fast internal reset after power-on.
Programmable Watchdog Timer
The watchdog timer in the C515C is a 15-bit timer, which is incremented by a count rate of f_OSC/6 up
to f_OSC/192. For programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog
timer can be written. Figure 23 shows the block diagram of the watchdog timer unit.
Figure 23
Block Diagram of the Programmable Watchdog Timer
The watchdog timer can be started by software (bit SWDT) or by hardware through pin PE/SWD,
but it cannot be stopped during active mode of the C515C. If the software fails to refresh the running
watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the
watchdog timer the content of the SFR WDTREL is transfered to the upper 7-bit of the watchdog
timer. The refresh sequence consists of two consequtive instructions which set the bits WDT and
SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined
by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the
idle mode and power down mode of the processor.
Semiconductor Group
50
1997-07-01