SDA9290-5 Datasheet, PDF (5/22 Pages) Siemens Semiconductor Group – Picture Processor

SDA 9290-5
Register R0: This control register sets the operating mode of the picture processor.
Bits D7, D6:
Mode
Normal
Multi-picture (MP)
Still-in-picture (SIP)
Picture-in still (PIS)
B1
B0
0
0
*D
0
1
1
0
1
1
Bit D5:
MPP: Narrow Frame
FR
Without narrow frame
0
With narrow frame
1
Bit D4:
No function; default 0
Bit D3:
Display Mode
Full screen
Split screen
SS
0 *D
1
Specialities:
Split Screen Display
For demonstration purposes the noise reduction can be disabled for half of the picture by means of
I²C Bus register R0, bit D3. In this way a direct comparison is possible between a noise-reduced
(filtered) and an unfiltered picture.
Bit D2:
Bit D1:
Bit D0:
Control of SNR adaptation
TV mode
VCR mode
Noise reduction ON/OFF
Noise reduction OFF
Noise reduction ON
Word width input
7 bits
8 bits
VCR
0 *D
1
NR
0 *D
1
SUV8
0
1
Semiconductor Group
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