SDA9290-5 Datasheet, PDF (2/22 Pages) Siemens Semiconductor Group – Picture Processor

SDA 9290-5
The necessary decimation and interpolation operations are activated automatically when the format
is set. Together with a corresponding Memory Sync Controller (SDA 9220) it enables functions like
multi-picture, tuner scanning, picture-in-still and still-in-picture. The different modes can be
activated by a microcontroller on the I²C Bus interface (slave receiver). The I²C Bus address for
accessing the device is
0
0
1
0
1
0
1
0
Circuit Description
The core of the picture processor (see block diagram) is formed of the Image-lmproving Processor
(IIP) and the Multi-Picture Processor (MPP). The IIP is responsible for noise and cross-color
reduction, while the MPP together with the new Memory Sync Controller implements the functions
multi-picture, tuner scanning, picture-in-still and still-in-picture.
Image-lmproving Processor
The signal inputs Yl0-YI7 and UVI0-UVI7 and the back-channel signal inputs YB0-YB7 and UVB0-
UVB7 picture data with 12 bits in quasi-parallel format (4:1:1) and with 16 bits in parallel format
(4:2:2). The clock rate for both signals is 13.5 MHz. For signal processing in the IIP and MPP the
chrominance bit levels have to be separated in the case of the quasi parallel format by
demultiplexers DEMUXS and DEMUXR, these being largely identical in design.
A reduction in video noise is achieved by correlating the picture contents of two successive fields,
the non-correlated components (noise) being attenuated by the digital filter. To achieve this, the
instantaneous digital picture signal on the outputs of the demultiplexer DEMUXS and the picture
signal delayed by a field interval on the outputs of the back-channel demultiplexer DEMUXR are fed
to the IIP and combined.
The signal-to-noise ratio (S/N) unit detects the noise components of the input signals and the
movement detector uses this information to select an appropriate set of parameters with filter
coefficients and thresholds for the comparators. For this purpose the luminance signal is assigned
to one of three classes according to its S/N ratio, with each class defining a different degree of
maximum noise reduction. The limits between the middle class and the upper and lower classes
can be programmed by the I²C Bus registers R1 and R2 with the values for the thresholds SU and
SL. When the picture signals come from a video cassette recorder, the adaptation on the S/N ratio
of the input signal should be disabled by I²L Bus register R0, VCR bit D2.
Measurement of the signal-to-noise ratio in the automatic mode has been advanced from line 7 to
line 6 in order to avoid conflicts with future text and data services.
The degree of noise reduction for the luminance and chrominance signals can be varied between
0 dB and 12 dB by selecting the appropriate filter coefficients.
A picture signal with reduced noise and cross-color appears on the output of the IIP for further
processing. The signal will be forwarded via blocks MUXI and MUXO to the picture memories
through the outputs (YQ0-YQ7 and UVQO-UVQ7 respectively).
The coefficients of the selected class are controlled by the movement detector as a function of
pixels to prevent artifacts (loss of focus) in moving parts of the picture.
Semiconductor Group
260