SDA9290-5 Datasheet, PDF (10/22 Pages) Siemens Semiconductor Group – Picture Processor

SDA 9290-5
Pin Definitions and Functions
Pin
No.
1
2-9
10
11-18
19-26
27-34
35-42
43
44
45
46
47
48
49
Symbol Function
Description
V_DD
Positive supply Positive supply voltage (+ 5 V)
voltage (+ 5 V)
UVQ7 … Data outputs
UVQ0
Push-pull outputs for directly driving the TV-SAM
chrominance inputs:
8 bits for 4:2:2 format;
4 bits for 4:1:1 format;
[UVQ0 … UVQ3 only valid for 4:2:2 format]
V_SS
UVB0 …
UVB7
Ground
Ground (0 V)
Back-channel data Back-channel inputs for chrominance data from TV-SAM
outputs
YB0 … Back- channel
YB7
data inputs
Back-channel inputs for luminance data from TV-SAM
UVI0 … Data inputs
UVI7
Data inputs for chrominance data accept the dig. YUV
signal
YI0 …
YI7
Data inputs
Data inputs for luminance data accept the dig. YUV
signal
DREQ
Data request
signal for multi-
picture mode
Data-request input; initiates data transfer in multi-picture
mode and switches mode together with signal VS1
V_SS
Ground
Ground (0 V)
BLN
Blanking signal Input for line-synchronous blanking signal that
(15.625 kHz)
determines line blanking interval (active low) and
synchronizes clock and sequence control
LLIN
First system clock Input for line-locked system clock, optionally 13.5 MHz or
(13.5 or 27 MHz) 27 MHz, from which internal timing is derived. Positive
edge indicates validity of input data
LLSEL
Selection of
system clock
frequency (LLIN)
Selection of input clock frequency at pin LLIN for
adapting the IC to the system clock. Low level for
27-MHz clock frequency; high level for 13.5-MHz clock
frequency; no switching inactive mode without picture
interference
LL3X
Second system
clock (13.5 MHz)
Input for line-locked 13.5-MHz clock that ensured picture
stability in multi-picture mode and is used as output clock
in every mode
SCL
I²C Bus shift clock I²C Bus shift-clock input
input
Semiconductor Group
268