SDA9290-5 Datasheet, PDF (18/22 Pages) Siemens Semiconductor Group – Picture Processor

SDA 9290-5
Figure 4
Timing for I²C Bus
All values are referred to specified input levels V_IH and V_IL.
Parameter
Symbol
Clock frequency
Inactive time before start of new transmission
Hold time for start condition
(after this time first clock pulse is generated)
Low clock phase
High clock phase
Setup time for data
Rise time for SDA and SCL signals
Fall time for SDA and SCL signals
Setup time for SCL clock in stop condition
f_SCL
t_BUF
t_{HD; STA}
t_LOW
t_HIGH
t_{SU; DAT}
t_TLH
t_THL
t_{SU; STO}
Limit Values Unit
min. max.
0
100
kHz
4.7
µs
4.0
µs
4.7
µs
4.0
µs
250
ns
1
µs
300
ns
4.7
µs
Semiconductor Group
276