C504 Datasheet, PDF (40/49 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

C504
AC Characteristics for C504-L / C504-2R (cont’d)
External Data Memory Characteristics
Parameter
RD pulse width
WR pulse width
Address hold after ALE
RD to valid data in
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR or RD
Address valid to WR or RD
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD
Symbol
Limit Values
Unit
12-MHz clock
Variable Clock
1/t_CLCL = 3.5 MHz to
12 MHz
t_RLRH
t_WLWH
t_LLAX2
t_RLDV
t_RHDX
t_RHDZ
t_LLDV
t_AVDV
t_LLWL
t_AVWL
t_WHLH
t_QVWX
t_QVWH
t_WHQX
t_RLAZ
min.
400
400
114
–
0
–
–
–
200
203
43
33
433
33
–
max.
–
–
–
252
–
97
517
585
300
–
123
–
–
–
0
min.
max.
6t_CLCL – 100 –
ns
6t_CLCL – 100 –
ns
2t_CLCL – 53 –
ns
–
5t_CLCL – 165 ns
0
–
ns
–
2t_CLCL – 70 ns
–
8t_CLCL – 150 ns
–
9t_CLCL – 165 ns
3t_CLCL – 50 3t_CLCL + 50 ns
4t_CLCL – 130 –
ns
t_CLCL – 40 t_CLCL + 40 ns
t_CLCL – 50 –
ns
7t_CLCL – 150 –
ns
t_CLCL – 50 –
ns
–
0
ns
External Clock Drive
Parameter
Oscillator period
High time
Low time
Rise time
Fall time
Symbol
Limit Values
Variable Clock
Freq. = 3.5 MHz to 12 MHz
t_CLCL
t_CHCX
t_CLCX
t_CLCH
t_CHCL
min.
83.3
20
20
–
–
max.
294
t t – _{CLCL CLCX}
t t – _{CLCL CHCX}
20
20
Unit
ns
ns
ns
ns
ns
Semiconductor Group
40