HYS64-74V8200GU Datasheet, PDF (16/17 Pages) Siemens Semiconductor Group – 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module

HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
SPD-Table for PC66 Modules (cont’d)
Byte# Description
SPD Entry Value
22 SDRAM Device Attributes: V_CC tol ± 10%
General
23 Min. Clock Cycle Time at 15.0 ns
CAS Latency = 2
24 Max. data access time from 9.0 ns
Clock for CL= 2
25 Minimum Clock Cycle Time not supported
at CL = 1
26 Maximum Data Access
not supported
Time from Clock at CL = 1
27 Minimum Row Precharge 30 ns
Time
28 Minimum Row Active to
Row Active delay t_RRD
20 ns
29 Minimum RAS to CAS delay 30 ns
t_RCD
30 Minimum RAS pulse width 45 ns
t_RAS
31 Module Bank Density (per 64 MByte
bank)
32 SDRAM input setup time 3 ns
33 SDRAM input hold time
1 ns
34 SDRAM data input hold time 3 ns
35 SDRAM data input setup 1 ns
time
62-61 Superset information
(may be used in future)
62 SPD Revision
Revision 1.2
63 Checksum for bytes 0 - 62
64- Manufacturers information
125 (optional)
(FF_H if not used)
126 Frequency Specification
66 MHz
127 Details
128+ Unused storage locations
Hex
8M×64 8M×72 16M×64 16M×72
-10 -10
-10
-10
06
06
06
06
F0
F0
F0
F0
90
90
90
90
FF
FF
FF
FF
FF
FF
FF
FF
1E
1E
1E
1E
14
14
14
14
1E
1E
1E
1E
2D
2D
2D
2D
10
10
10
10
30
30
30
30
10
10
10
10
30
30
30
30
10
10
10
10
FF
FF
FF
FF
12
12
12
12
B0
C2
B1
C3
XX
XX
XX
XX
66
66
66
66
AF
AF
FF
FF
FF
FF
FF
FF
Semiconductor Group
16
1998-08-01