HYS64-74V8200GU Datasheet, PDF (14/17 Pages) Siemens Semiconductor Group – 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module

HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
SPD-Table for PC100 Modules (cont’d)
Byte# Description
SPD
Entry
Value
Hex
8M×64 8M×64 8M×72 16M×64 16M×64 16M×72
-8
-8B
-8
-8
-8B
-8
29 Minimum RAS to 20 ns
14
14
14
14
14
14
CAS delay t_RCD
30 Minimum RAS
45 ns
2D 2D 2D 2D
2D
2D
pulse width t_RAS
31 Module Bank
64 MByte 10
10
10
10
10
10
Density (per bank)
32 SDRAM input setup 2 ns
time
20
20
20
20
20
20
33 SDRAM input hold 1 ns
time
10
10
10
10
10
10
34 SDRAM data input 2 ns
hold time
20
20
20
20
20
20
35 SDRAM data input 1 ns
setup time
10
10
10
10
10
10
62-61 Superset
–
information (may
be used in future)
FF
FF
FF
FF
FF
FF
62 SPD Revision
Revision 12
12
12
12
12
12
1.2
63 Checksum for
–
bytes 0 - 62
D8
16
EA D9
17
EB
64- Manufacturers
–
XX XX XX XX
XX
XX
125 information
(optional)
(FF_H if not used)
126 Frequency
100 MHz 64
64
64
64
64
64
Specification
127 100 MHz support –
details
AF AD AF FF
FD
FF
128+ Unused storage
–
locations
FF
FF
FF
FF
FF
FF
Semiconductor Group
14
1998-08-01