HYS64-74V8200GU Datasheet, PDF(15/17 Page) Siemens Semiconductor Group – 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module

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HYS64-74V8200GU Datasheet, PDF (15/17 Pages) Siemens Semiconductor Group – 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module

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HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

SPD-Table for PC66 Modules

Byte# Description

Number of SPD bytes

Total bytes in Serial PD

Memory Type

Number of Row Addresses

(without BS bits)

Number of Column

Addresses

(for x8 SDRAM)

Number of DIMM Banks

Module Data Width

Module Data Width (contâd)

Module Interface Levels

SDRAM Cycle Time at

CL = 3

10 SDRAM Access time from

Clock at C L= 3

11 Dimm Config

(Error Det/Corr.)

12 Refresh Rate/Type

13 SDRAMwidth,Primary

14 Error Checking SDRAM

data width

15 Minimum clock delay for

back-to-back random

column address

16 Burst Length supported

17 Number of SDRAM banks

18 Supported CAS Latencies

19 CS Latencies

20 WE Latencies

21 SDRAM DIMM module

attributes

SPD Entry Value

128

256

SDRAM

1/2

64/72

LVTTL

10.0 ns

8.0 ns

none/ECC

Self Refresh

15.6 Âµs

Ã8

n/a/Ã8

tCCD = 1 CLK

1, 2, 4, 8 & full page

CAS latency = 2 & 3

CS latency = 0

Write latency = 0

non buffered/

non reg.

Hex

8MÃ64 8MÃ72 16MÃ64 16MÃ72

-10 -10

-10

Semiconductor Group

1998-08-01

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