LQ104V1DG51 Datasheet, PDF (9/21 Pages) Sharp Electrionic Components – TFT LCD MODULE

LD13708-7
7. Timing Characteristics of input signals
Timing diagrams of input signal are shown in Fig.2 - ①～③　.
7-1. Timing characteristics
Parameter
Symbol Mode Min. Typ. Max. Unit Remark
Clock
Frequency 1/Tc all
－ 25.18 28.33 MHz
High time Tch 〃
5
－
－
ns
Low time Tcl 〃
10
－
－
ns
Data
Setup time Tds 〃
5
－
－
ns
Hold time Tdh 〃
10
－
－
ns
Horizontal Cycle
TH 〃 30.00 31.78 － μs
sync. signal
〃 770 800 900 clock
Pulse width THp 〃
2
96
200 clock
Vertical
Cycle
TV 480 515 525 560 line
sync. signal
400 445 449 480 line
350 447 449 510 line
Pulsewidth TVp all
1
－
34 line
Horizontal display period THd 〃 640 640 640 clock
Hsync-Clock
THc 〃
10
－ Tc-10 ns
phase difference
Hsync-Vsync
TVh 〃
0
－ TH-THp clock
phase difference
Note) In case of lower frequency, the deterioration of display quality, flicker etc.,may be occurred.
7-2. Horizontal display position
The horizontal display position is determined by ENAB signal and the input data corresponding
to the rising edge of ENAB signal is displayed at the left end of the active area.
Parameter
symbol Min. Typ. Max. Unit Remark
Enable signal Setup time Tes
5
－ Tc-10 ns
Pulse width Tep
2
640 640 clock
Hsync-Enable signal
THe 44
－ TH-664 clock
phase difference
Note) When ENAB is fixed "Low", the display starts from the data of C104(clock) as shown
in Fig.2-①～③. Be careful that the module does not work when ENAB is fixed "High".
When the phase difference is below 104 clock, keep the “High level of ENAB is signal longer
Than 104-The. If it will not be keeped, the display starts from the data of C104(clock).