LRS1381 Datasheet, PDF (75/114 Pages) Sharp Electrionic Components – STACKED CHIP 32M FLASH AND 4M SRAM

FUM00701
29
Bus
Operation
Command
Comments
Write
Full Chip
Erase
<First cycle>
Data=30H
Addr=X
<Second cycle>
Data=D0H
Addr=X
Read
Status Register Data
Addr=X
Standby
Check SR.7
1=WSM Ready
0=WSM Busy
Check the status after full chip erase.
Write FFH after the full chip erase to place device in read
array mode.
Bus
Operation
Command
Comments
Write
Read Status Data=70H
Register Addr=Within Partition
Read
Status Register Data
Addr=Within Partition
Standby
Check SR.7
1=WSM Ready
0=WSM Busy
Standby
Check SR.6
1=Block Erase Suspended
0=Block Erase Completed
Standby
Check SR.2
1=(Page Buffer) Program
Suspended
0=(Page Buffer) Program
Completed
Figure 6.1. Automated Full Chip Erase Flowchart
|||||||||||||||||||R||||||e||R||v|||.e|||v|2||||.||2||||.0||2||||0||||||||||||||||
Appendix to Spec No.: MFM2-J13318 Model No.: LRS1381 March 16, 2001