LRS1381 Datasheet, PDF (21/114 Pages) Sharp Electrionic Components – STACKED CHIP 32M FLASH AND 4M SRAM

LRS1381
19
Symbol
Parameter
DC Electrical Characteristics (Continue)
(T_A = -25°C to +85°C, V_CC = 2.7V to 3.3V)
Notes Min. _Typ.⁽¹⁾ Max. Unit
Conditions
I_SB S-V_CC Standby Current
2
25
µA
S-CE₁, S-CE₂
S-CE₂ 0.2V
S-V_CC - 0.2V or
I_SB1 S-V_CC Standby Current
3 mA ^S-CE2 ^{= V}IL
I_CC1 S-V_CC Operation Current
S-CE₁ = V_IL,
50 mA S-CE₂ = V_IH
V_IN = V_IL or V_IH
t_CYCLE = Min
I_I/O = 0mA
I_CC2 S-V_CC Operation Current
8
mA
S-CE₁
S-CE
0.2V,
S-V_CC -0.2V, ^tCYCLE ^{= 1µA}
V_IN S-V_CC -0.2V I_I/O = 0mA
or 0.2V
V_IL Input Low Voltage
V_IH Input High Voltage
6 -0.2
VCC
6 _-0.4
0.4 V
VCC
+0.2 ^V
V_OL Output Low Voltage
6
0.4 V I_OL = 0.5mA
V_OH Output High Voltage
6
V_CC
-0.2
V I_OH = -0.5mA
V_PPLK
F-V_PP Lockout during Normal
Operations
4,6,7
0.4 V
V_PPH1 F-V_PP during Block Erase, Full Chip
1.65 3 3.3 V
Erase, Word Write or Lock-Bit
V_{PPH2 configuration Operations}
7 11.7 12 12.3 V
V_LKO F-V_CC Lockout Voltage
1.5
V
Notes:
1. V_CC includes both F-V_CC and S-V_CC.
2. All currents are in RMS unless otherwise noted. Typical values at nominal V_CC voltage and T_A=+25 C.
3. I_CCWS and I_CCES are specified with the device de-selected. If read or (page buffer) program while in block erase suspend
mode, the device’s current draw is the sum of I_CCWS or I_CCES and I_CCR or I_CCW, respectively.
4. Block erase, full chip erase, (page buffer) program and OTP program are inhibited when F-V_PP V_PPLK, and not
guaranteed in the range between V_PPLK (max.) and V_PPH1 (min.) , between V_PPH1 (max.) and V_PPH2 (min.) and above
V_PPH2 (max.).
5. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle
completion. Standard address access timings (t_AVQV) provide new data when addresses are changed.
6. Sampled, not 100% tested.
7. F-V_PP is not used for power supply pin. With F-V_PP V_PPLK, block erase, full chip erase, (page buffer) program and OTP
program cannot be executed and should not be attempted.
Applying 12V ±0.3V to F-V_PP provides fast erasing or fast programming mode. In this mode, F-V_PP is power supply pin
and supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace
widths and layout considerations given to the V_CC power bus.
Applying 12V ±0.3V to F-V_PP during erase/program can only be done for a maximum of 1000 cycles on each block.
F-V_PP may be connected to 12V ±0.3V for a total of 80 hours maximum.