LRS1381 Datasheet, PDF (36/114 Pages) Sharp Electrionic Components – STACKED CHIP 32M FLASH AND 4M SRAM

LRS1381
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15. Notes
This product is a stacked CSP package that a 32M (x16) bit Flash Memory and a 4M (x16) bit SRAM are assembled into.
- Supply Power
Maximum difference (between F-V_CC and S-V_CC) of the voltage is less than 0.3V.
- Power Supply and Chip Enable of Flash Memory and SRAM (F-CE, S-CE₁, S-CE₂)
S-CE₁ should not be “low” and S-CE₂ should not be “high” when F-CE is “low” simultaneously.
If the two memories are active together, possibly they may not operate normally by interference noises or data collision
on DQ bus.
Both F-V_CC and S-V_CC are needed to be applied by the recommended supply voltage at the same time expect SRAM
data retention mode.
- Power Up Sequence
When turning on Flash memory power supply, keep F-RST “low”. After F-V_CC reaches over 2.7V, keep F-RST “low”
for more than 100nsec.
- Device Decoupling
The power supply is needed to be designed carefully because one of the SRAM and the Flash Memory is in standby
mode when the other is active. A careful decoupling of power supplies is necessary between SRAM and Flash
Memory. Note peak current caused by transition of control signals (F-CE, S-CE₁, S-CE₂).