ID242 Datasheet, PDF (16/33 Pages) Sharp Electrionic Components – Flash Memory Card

SHARI=
ID242 SERIES PRODUCT OVERVIEW
15
9. 5 Write Protection Register (Address:4104h)
Address
Bit.7
4104h
Bit.6
Bit.5
Bit.4
Reserved
Bit.3
Bit.2
Bit.1
BLKBN
CMWP
BLKBN:
CMWP:
CISWP:
Block Locking Enable
1 = Enable Block Locking 0 = All Blocks Unlocked
Common Memory Write Protect
1 = Common Memory without CIS region in Write Protect Status
Common Memory CIS Write Protect
I = Common Memory CIS in Write Protect Status
NOTE: ID242 series ignores BLKBN bit. Block Locking is always enable.
Bit.0
CISWP
9. 6 Sleep Control Register (Address:4118h-411 Ah)
Address
Bit.7
Bit.6
Bit.5
Bit.4
Bit.3
Bit.2
Bit. 1
Bit.0
4llAh
Reserved
4118h
Reserved
DEVlO/ll
DEV8/9
DEV6/7
DEV4/5
DEV2/3
DEVO/l
1= Select sleep mode device-pair
If set to “l”, the corresponding device-pairs are putted into deep power-down
by PWDN bit of Configuration Status Register.
mode
Tl047.01
9. 7 Ready/Busy Mask Register (Address:4120h-4122h)
Address
Bit.7
Bit.6
Bit.5
Bit.4
Bit.3
Bit.2
Bit. 1
Bit.0
412231
Reserved
DEVll
DEVlO
DEV9
DEV8
4120h
DEV7
DEV6
DEV5
DEV4
DEV3
DEV2
DEVl
DEVO
1 =Mask the RdylBsy#
The corresponding device’s Rdy/Bsy# signals to set bit are ignored for card’s
RDY/BSY# output.
T1040.01
9. 8 Ready/Busy Status Register (Address:4130h-4132h)
Address
Bit.7
Bit.6
Bit.5
Bit.4
Bit.3
Bit.2
4132h
Reserved
DEVll
DEVlO
4130h
DEV7
DEV6
DEV5
DEV4
1 =READY
O=BUSY
Each bit indicates the corresponding
DEV3
DEV2
device’s Rdy/Bsy# signal.
Bit. 1
DEV9
DEVl
Bit.0
DEV8
DEVO
Tl041.01
9. 9 Ready/Busy Mode Register (Address:4140h)
Address
Bit.7
Bit.6
Bit.5
Bit.4
Bit.3
Bit.2
Bit. 1
Bit.0
4140h
RACK:
MODE:
Reserved
RACK
MODE
Ready Acknowledge Bit
Must-clear this bit after receiving ready status to prepare for next device’s ready
transition.
RDY/BSY# Mode
1 = High-Performance Mode 0 = PCMCIA Mode
T1055.01
CPS0002-002@May.l99i