ID242 Datasheet, PDF (14/33 Pages) Sharp Electrionic Components – Flash Memory Card

SHARP
ID242 SERIES PRODUCT OVERVIEW
13
Table 7. Status Register
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SR.7
SR.6
SR.5
SR.4
SR.3
SR.2
SR.l
SR.0
WSMS
ESS
ECLBS
BWSLBS
VPPS
BWSS
DPS
RFU
SR.7 =WRITE STATE MACHINE STATUS
I = Ready
0 = Busy
SR.6 =ERASE-SUSPEND STATUS
I = Erase Suspended
0 = Erase in Progress/Completed
SR.5 =ERASE AND CLEAR LOCK-BlTS STATUS
1 = Error ln Block Erasure or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
SR.4 =BYTE WRITE AND SET LOCK-BIT
1 = Error in Byte Write or
Set Block/Master Lock-Bit
0 = Successful Byte Write or
Set Block/Master Lock-Bit
STATUS
SR.3 =VPP STATUS
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.2 =BYTE WRITE SUSPEND STATUS
1 = Byte Write Suspended
0 = Byte Write in Progress/Completed
SR. 1 =DEVICE PROTECT STATUS
1 = Master Lock-bit,Block Lock-bit and/or
RP# Lock Detected, Operation Abort
0 = Unlock
SR.0 =Reserved for Future Enhancements
Notes:
Chech RDY/BSY# or SR.7 to determine block erase,
word/byte write, or lock-bit configuration completion.
SR.6-0 are invalid while SR.7=“0”.
If both SR.5 and SR.4 are ” 1“s after a block erase or lock-
bit configuration attempt, an improper command
sequence was entred.
SR.3 does not provide a continuous indication of V,,
level. The WSM interrogates and indicates the V,, level
only after Block Erase, Word/Byte Write, Set
Block/Master Lock-bit, or Clear Lock-bits command
sequences. SR.3 is not guaranteed to reports accurate
feedback only when V,,=V,,,,,,,,.
SR. 1 does not provide a continuous indication of master
and block lock-bit values. The WSM interrogates the
master lock-bit, block lock-bit. and RP# only after Block
Erase, Word/Byte Write, or Lock-bit configuration
command sequences. If informs the system, depending
on the attempted operation, if the block lock-bit is set,
master lock-bit is set, and/or RP# is not 12V. Reading
the block lock and master lock configuration codes after
writing the Read Identifier Codes commnad indicates
master and block lock-bit status.
SR.0 is reserved for future use and should be masked out
when polling the status register.
Table 8. Identifier Codes / Lock bits
Block Lock
Configuration
(X: Select Block)
D7-D I: Reserved
NOTE: A0 is ignored in word access mode. and D15-D8 outputs the Odd byte data.
DPA: Address as select device pair
BLKD: Block Lock Configuration Data
MLKD: Master Lock Configuration Data
T1052-01
CPSOOO2-0028
May. 1999