100E016 Datasheet, PDF (5/9 Pages) SEMTECH ELECTRONICS LTD. – 8-Bit Synchronous Binary Up Counter

SK10/100E016
HIGH-PER.ORMANCE PRODUCTS
Application Information (continued)
A single E016 can be used to divide by any ratio from 2
to 256 inclusive. If divide ratios of greater than 256
are needed, multiple E016s can be cascaded in a
manner similar to that already discussed. When E016s
are cascaded to build larger dividers, the TCLD pin will
no longer provide a means for loading on terminal count.
Because one does not want to reload the counters until
all of the devices in the chain have reached terminal
count, external gating of the TC* pins must be used for
multiple E016 divider chains.
Figure 6 shows a typical block diagram of a 32-bit divider
chain. Once again, to maximize the frequency of
operation, EL01 OR gates were used. For lower
frequency applications, a slower OR gate could replace
the EL01. Note that for a 16-bit divider, the OR function
feeding the PE* (program enable) input CANNOT be
placed by a wire OR tie as the TC* output of the least
significant E016 must also feed the CE* input of the
most significant E016. If the two TC* outputs were OR
tied, the cascaded count operation would not operate
properly. Because, in the cascaded form, the PE*
feedback is external and requires external gating, the
maximum frequency of operation will be significantly less
than the same operation in a single device.
Maximizing E016 Count Frequency
The E016 device produces 9 fast transitioning single-
ended outputs, thus VCC noise can become significant
in situations where all of the outputs switch
simultaneously in the same direction. This VCC noise
can negatively impact the maximum frequency of
operation of the device. Since the device does not
need to have the Q outputs terminated to count properly,
it is recommended that if the outputs are not going to
be used in the rest of the system, they should be
terminated. Not terminating the unused outputs will
not only cut down the VCC noise generated, but will
also save in total system power dissipation. Following
these guidelines will allow designers to either be more
aggressive in their designs or provide them with an
extra margin to the published databook specifications.
CLOCK
PE*
TC*
LOAD
1001 0000 1001 0001 1111 1100 1111 1101 1111 1110 1111 1111
LOAD
DIVIDE BY 113
Figure 5. Divide by 113 E016 Programmable Divider Waveforms
Revision 1/.ebruary 13, 2001
5
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