100E016 Datasheet, PDF (4/9 Pages) SEMTECH ELECTRONICS LTD. – 8-Bit Synchronous Binary Up Counter

SK10/100E016
HIGH-PER.ORMANCE PRODUCTS
Application Information (continued)
LOAD
® Q0 Q7
CE*
PE*
E016
LSB
® Q0 Q7
CE*
PE*
E016
® Q0 Q7
CE*
PE*
E016
CLK TC*
® P0 P7
CLK TC*
® P0 P7
EL01
CLK TC*
® P0 P7
CLOCK
Figure 3. 32-Bit Cascaded E016 Counter
EL01
® Q0 Q7
CE*
PE*
E016
MSB
CLK TC*
® P0 P7
Programmable Divider
The E016 has been designed with a control pin which
makes it ideal for use as an 8-bit programmable divider.
The TCLD pin (load on terminal count) when asserted
reloads the data present at the parallel input pin (Pn’s)
upon reaching terminal count (an all 1s state on the
outputs). Because this feedback is built internal to the
chip, the programmable division operation will run at very
nearly the same frequency as the maximum counting
frequency of the device. Figure 4 below illustrates the
input conditions necessary for utilizing the E016 as a
programmable divider set up to divide by 113.
HL L LHHHH
P7 P6 P5 P4 P3 P2 P1 P0
H
PE*
L
CE*
H
TCLD
CLK
TC*
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Figure 4. Mod 2 to 256 Programmable Divider
To determine what value to load into the device to
accomplish the desired division, the designer simply
subtracts the binary equivalent of the desired divide ratio
from the binary value for 256. As an example for a divide
ratio of 113:
Revision 1/.ebruary 13, 2001
4
Pn’s = 256 – 113 = 8F₁₆ = 1000 1111
where:
PO = LSB and P7 = MSB
Forcing this input condition as per the setup in Figure
4 will result in the waveforms of Figure 5. Note that
the TC* output is used as the divide output and the
pulse duration is equal to a full clock period. For
even divide ratios, twice the desired divide ratio can
be loaded into the E016, and the TC* output can
feed the clock input of a toggle flip-flop to create a
signal divided as desired with a 50% duty cycle.
Divide
Ratio
2
3
4
5
l
l
112
113
114
l
l
254
255
256
Preset Data Inputs
P7 P6 P5 P4 P3 P2 P1 P0
HHHHHHHL
HHHHHHL H
HHHHHHL L
HHHHHL HH
llllllll
llllllll
HL LHL L L L
HL L L HHHH
HL L L HHHL
llllllll
llllllll
L L L L L LHL
LLLLLLLH
LLLLLLLL
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