GS2960 Datasheet, PDF (89/97 Pages) Semtech Corporation – 3Gb/s, HD, SD SDI Receiver Complete with SMPTE Video Processing

Table 4-17: Configuration and Status Registers (Continued)
Address Register Name Bit Name
06Dh
IO_DRIVE
_STRENGTH
RSVD
IO_DS_CTRL_DOUT_MSB
IO_DS_CTRL_STAT
IO_DS_CTRL_DOUT_LSB
06Eh
06Fh
070h
-085h
RSVD
RSVD
M_DETECTION
_TOLERANCE
RSVD
RSVD
RSVD
M_DETECTION
_TOLERANCE
RSVD
Bit Description
15-6
5-4
3-2
1-0
15-0
15-4
3-0
Reserved.
Drive strength adjustment for
DOUT[19:10] outputs and PCLK
output:
00: 4mA;
01: 8mA;
10: 10mA(1.8V), 12mA(3.3V);
11: 12mA(1.8V), 16mA(3.3V)
Drive strength adjustment for
STAT[5:0] outputs:
00: 4mA;
01: 6mA;
10: 8mA(1.8V), 10mA(3.3V);
11: 10mA(1.8V), 12mA(3.3V)
Drive strength adjustment for
DOUT[9:0] outputs:
00: 4mA;
01: 6mA;
10: 8mA(1.8V), 10mA(3.3V);
11: 10mA(1.8V), 12mA(3.3V)
Reserved.
Reserved.
Sets the detection tolerance.
15-0 Reserved.
R/W
R/W
R/W
Default
0
2
R/W
2
R/W
3
R/W
0
R/W
0
R/W
2
R/W
0
Table 4-18: ANC Extraction FIFO Access Registers
Address
Register Name
Bit
800h -
BFFh
ANC_PACKET_BANK
15-0
Description
Extracted Ancillary Data 91024 words.
Bit 15-8: Most Significant Word (MSW).
Bit 7-0: Least Significant Word (LSW).
See Section 4.18.8.
4.21 JTAG Test Operation
When the JTAG/HOST pin of the GS2960 is set HIGH, the host interface port is
configured for JTAG test operation. In this mode, pins E7, F8, F7, and E8 become TDO,
TCK, TMS, and TDI. In addition, the RESET_TRST pin operates as the test reset pin.
Boundary scan testing using the JTAG interface is enabled in this mode.
There are two ways in which JTAG can be used:
1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test
Equipment) during PCB assembly.
R/W
R
Default
0
GS2960 3Gb/s, HD, SD SDI Receiver Complete with
SMPTE Video Processing
Data Sheet
48003 - 6
September 2012
89 of 97