GS2960 Datasheet, PDF (38/97 Pages) Semtech Corporation – 3Gb/s, HD, SD SDI Receiver Complete with SMPTE Video Processing

Table 4-6: GS2960 PCLK Output Rates (Continued)
Output Data
Format
10-bit data output
SD format
10-bit ASI output
SD format
20bit/
10bit
LOW
LOW
Pin/Control Bit Settings
RATE_DET0 RATE_DET1
HIGH
−
SMPTE_
BYPASS
LOW
HIGH
−
LOW
DVB-ASI
LOW
HIGH
4.9.6 DDR Parallel Clock Timing
The GS2960 has the ability to transmit 10-bit parallel video data with a DDR (Dual Data
Rate) pixel clock over a single-ended interface. DDR Mode can be enabled when the SDI
data bandwidth is 3Gb/s. In this case, the 10-bit parallel data rate is 297Mb/s, and the
frequency of the DDR clock is 148.5MHz (10-bit output in 3G mode).
The DDR pixel clock avoids the need to operate a high-drive pixel clock at 297MHz. This
reduces power consumption, clock drive strength, and noise generation. It also enables
easier board routing and avoids the need to use the higher-speed I/Os on FPGAs, which
may require more expensive speed grades.
Figure 4-7 shows how the DDR interface operates. The pixel clock is transmitted at half
the data rate, and the interleaved data is sampled at the receiver on both clock edges.
PCLK Rate
27MHz
27MHz
20-bit bus
(transition rate = 74.25MHz)
10-bit bus
(transition rate = 148.5MHz)
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Cb0
Cr0
Cb1
Cr1
Cb2
Cr2
Cb3
Cr3
Cb4
Cr4
Y0
Cb
0
Y1
Cr
0
Y2
Cb
1
Y3
Cr
1
Y4
Cb
2
Y5
Cr
2
Y6
Cb
3
Y7
Cr
3
Y8
Cb
4
Y9
Cr
4
PCLK
(148.5MHz)
Figure 4-7: DDR Video Interface
The GS2960 has the ability to shift the Setup/Hold window on the receive interface, by
using an on-chip delay line to shift the phase of PCLK with respect to the data bus.
The timing of the PCLK output, relative to the data, can be adjusted through the host
interface registers. Address 06Ch contains the delay line controls:
Bit[5] (DEL_LINE_CLK_SEL) is a coarse delay adjustment that selects between the
default (nominal) PCLK phase and a quadrature phase, for a 90º phase shift.
Bits[4:0] (DEL_LINE_OFFSET) comprise a fine delay adjustment to shift the PCLK in
40ps increments (typical conditions). The maximum fine delay adjustment is
approximately 1.2ns under nominal conditions.
GS2960 3Gb/s, HD, SD SDI Receiver Complete with
SMPTE Video Processing
Data Sheet
48003 - 6
September 2012
38 of 97