GS2970 Datasheet, PDF (83/145 Pages) Semtech Corporation – 3Gb/s, HD, SD SDI Receiver Complete with SMPTE Audio and Video Processing

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
24-bit array
ADF ADF ADF DID DBN DC CLK CLK CH1 CH1 CH1 CH1 CH2 CH2 CH2 CH2 CH3 CH3 CH3 CH3 CH4 CH4 CH4 CH4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Errors corrected
ADF ADF ADF DID DBN DC CLK CLK CH1 CH1 CH1 CH1 CH2 CH2 CH2 CH2 CH3 CH3 CH3 CH3 CH4 CH4 CH4 CH4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Errors detected but not corrected
Figure 4-41: ECC 24-bit Array and Examples
4.19.3 Audio Processing
4.19.3.1 Audio Clock Generation
For SD and HD/3G audio, a single set of audio frequencies is generated for all audio
channels, using a Direct Digital Period Synthesizer (DDPS) to minimize jitter.
• For Mapping structure one signals (1080p 50, 59.94 or 60), the pixel clock is
148.5(/M) MHz, and the phase data are based on this rate. An Audio Master Clock
(AMCLK) is also generated. The frequency is selectable via the host interface as:
Š fs x 128
Š fs x 256
Š fs x 512
In SD mode, audio clocks are derived from the PCLK.
In HD/3G modes, the input control for the DDPS is derived from the two embedded
audio clock phase words in the audio data packet corresponding to Group A. The audio
clock phase information used is taken from the first embedded audio packet in the
HANC space. With no embedded audio present, the device will not generate ACLK or
WCLK. The IGNORE_PHASE bit should be asserted in this case to ensure the proper
AMCLK frequency is generated.
The audio de-embedder also includes a Flywheel block to overcome any inconsistencies
in the embedded audio clock phase information.
If the audio phase data is not present in the audio data packets, or is incorrect, the
NO_PHASEA_DATA bit in the host interface is set and the clock will free-run based on
the detected video format, the PCLK and the M value. IGNORE_PHASE should be set
HIGH when NO_PHASEA_DATA is set. This does not occur automatically.
When the IGNORE_PHASE bit in the host interface is set HIGH, it is recommended that
the M value be programmed via the host interface. This can be done by setting the
GS2970 3Gb/s, HD, SD SDI Receiver Complete with
SMPTE Audio and Video Processing
Data Sheet
47478 - 4
September 2012
83 of 145