GS2970 Datasheet, PDF (42/145 Pages) Semtech Corporation – 3Gb/s, HD, SD SDI Receiver Complete with SMPTE Audio and Video Processing

NOTE: For correct operation of the timing signal generator, the SW_EN input pin must
be set LOW, unless manual synchronous switching is enabled (Section 4.10.1).
4.10.1 Manual Switch Line Lock Handling
The principle of switch line lock handling is that the switching of synchronous video
sources will only disturb the horizontal timing and alignment, whereas the vertical
timing remains in synchronization - i.e. switching between video sources of the same
format.
To account for the horizontal disturbance caused by a synchronous switch, the word
alignment block and timing signal generator automatically re-synchronizes to the new
timing immediately if the synchronous switch happens during the designated switch
line, as defined in SMPTE recommended practice RP168-2002.
The device samples the SW_EN pin on every PCLK cycle. When a Logic LOW to HIGH
transition on this pin is detected anywhere within the active line, the word alignment
block and timing signal generator re-synchronize immediately to the next TRS word.
This allows the system to force immediate lock on any line, if the switch point is
non-standard.
To ensure proper switch line lock handling, the SW_EN signal should be asserted HIGH
anywhere within the active portion of the line on which the switch has taken place, and
should be held HIGH for approximately one video line. After this time period, SW_EN
should be de-asserted. SW_EN should be held LOW during normal device operation.
NOTE: It is the rising edge of the SW_EN signal, which generates the switch line lock
re-synchronization. This edge must be in the active portion of the line containing the
video switch point.
GS2970 3Gb/s, HD, SD SDI Receiver Complete with
SMPTE Audio and Video Processing
Data Sheet
47478 - 4
September 2012
42 of 145