GS4915 Datasheet, PDF (6/27 Pages) Gennum Corporation – ClockCleaner™

1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Number
1
Name
REG_VDD
2, 6, 9, 26, AGND
30, 31, 40
3
PD_VDD
4, 5
CLKIN, CLKIN
7
IN_VDD
8
CLKIN_SE
10
RESET
11
IPSEL
12, 20, 22 GND
13
BYPASS
14
AUTOBYPASS
15
D_VDD
17, 16 FCTRL1, FCTRL0
Timing
Type Description
–
–
–
–
–
–
Non
synchronous
Non
synchronous
–
Non
synchronous
Non
synchronous
–
Non
synchronous
Power
Power
Power
Input
Power
Input
Input
Input
Power
Input
Input
Power
Input
Positive power supply connection for the internal voltage regulator.
Connect to filtered +3.3V DC.
Ground connection for analog blocks and IOs. Connect to clean analog
GND.
Positive power supply connection for the phase detector. Connect to
filtered +1.8V DC.
CLOCK SIGNAL INPUTS
Signal levels are CML/LVDS compatible.
A differential clock input signal is applied to these pins.
Positive power supply connection for the single-ended and differential
input clock buffers. Supplies CLKIN_SE. Connect to filtered +1.8V DC.
CLOCK SIGNAL INPUT
Signal levels are LVCMOS compatible.
A single-ended video clock input signal is applied to this pin.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
See Section 3.8.1 for operation.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS compatible.
Selects which input clock is cleaned by the device.
See Section 3.2.3 for operation.
Ground connection for digital blocks and IO’s. Connect to GND.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS compatible.
See Manual Bypass Section 3.4.2.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS compatible.
Selects the bypass mode of the device.
See Manual Bypass Section 3.4.2.
Positive power supply connection for digital block. Connect to filtered
+1.8V DC. The digital block includes pins 10 - 21.
CONTROL SIGNAL INPUTS
Signal levels are LVCMOS compatible.
Selects the frequency mode of the device.
See Section 3.4.1 for operation.
GS4915 ClockCleaner™
Data Sheet
39145 - 5
June 2009
6 of 27