GS4915 Datasheet, PDF (20/27 Pages) Gennum Corporation – ClockCleaner™

Table 3-6: Output Behaviour in Forced Output Mode
FCTRL[1:0]
Input
DOUBLE
LOCK
Output
Auto [00]
27MHz
X
HIGH
27MHz
74.25MHz
0
HIGH
74.25MHz
1
HIGH
148.5MHz
148.5MHz
X
HIGH
148.5MHz
Other
X
LOW
Last locked*
Fixed – 27MHz
27MHz
X
HIGH
27MHz
[01]
74.25MHz
X
LOW
27MHz
148.5MHz
X
LOW
27MHz
Other
X
LOW
27MHz
Fixed –
74.25MHz [10]
27MHz
0
LOW
74.25MHz
1
LOW
148.5MHz
74.25MHz
0
HIGH
74.25MHz
1
HIGH
148.5MHz
148.5MHz
0
LOW
74.25MHz
1
LOW
148.5MHz
Other
0
LOW
74.25MHz
1
LOW
148.5MHz
Fixed –
27MHz
X
LOW
148.5MHz
148.5MHz [11]
74.25MHz
X
LOW
148.5MHz
148.5MHz
X
HIGH
148.5MHz
Other
X
LOW
148.5MHz
*NOTE: The output clock will remain within ± 5% of the last locked frequency if an input
frequency other than 27MHz, 74.25MHz, or 148.5MHz is applied to the selected clock input. If
operating under these conditions upon power-up, the output frequency will be 74.25MHz ±
5%.
3.6 Output Skew
The GS4915 provides the user with the option of advancing the phase of the output clock
from that of the input clock. This feature is controlled by the external SKEW_EN pin.
When SKEW_EN is set LOW, the output clock will be delayed from the selected input
clock only by the latency of the device. By setting SKEW_EN = HIGH, the user can
advance the output clock from the selected input clock by one quarter of an output
period, minus the latency of the device. Please see Figure 3-2.
GS4915 ClockCleaner™
Data Sheet
39145 - 5
June 2009
20 of 27