GS4915 Datasheet, PDF (15/27 Pages) Gennum Corporation – ClockCleaner™

Table 3-1: Loop Filter Component Values
Loop Filter
R
Typical Loop
Bandwidth*
Recommended
Loop Filter C
Comments
1Ω
2kHz
33μF
7Ω
8kHz
10μF
20Ω
40kHz
1μF
Note:
1. *Measured with 300ps pk-pk input jitter on CLK.
Narrow bandwidth - provides maximum jitter reduction. Long lock-time.
Wide bandwidth. Fast lock-time.
3.3.4 External VCO
The GS4915 uses the external GO1555 Voltage Controlled Oscillator as part of its
phase-locked loop. This external VCO implementation was chosen to ensure superior
jitter performance of the device.
Power for the external VCO is generated entirely by the GS4915 from an on-chip voltage
regulator. The internal regulator uses +3.3V DC supplied at the REG_VDD pin to provide
+2.5V at the VCO_VDD pin.
Based on the control voltage output by the GS4915 on the LF pin, the GO1555 produces
a 1.485GHz reference signal for the PLL. This signal must be run via a 50Ω
controlled-impedance trace to the VCO pin of the GS4915. The VCO receiver block of
the device will then convert this single-ended signal into the differential 1.485GHz
reference signal used by the clock cleaning PLL.
Both the reference and controls signals should be referenced to the supplied VCO_GND,
as shown in the recommended application circuit of the Typical Application Circuit on
page 22.
3.4 Modes of Operation
The GS4915 may operate in one of two possible frequency modes, and in one of three
possible bypass modes. The combination of the frequency mode and bypass mode will
determine the frequency and jitter of the output clock.
3.4.1 Frequency Modes
The frequency mode of the device is determined entirely by the setting of the external
FCTRL[1:0] pins.
Table 3-2: GS4915 Frequency Modes
FCTRL[1:0]
00
01
Frequency Mode
Auto
Fixed – 27MHz ± 0.4%
GS4915 ClockCleaner™
Data Sheet
39145 - 5
June 2009
15 of 27