LV24100LP Datasheet, PDF (8/18 Pages) Sanyo Semicon Device – Bi-CMOS IC FM and AM Tuner IC for Small Portable Equipment

• External clock timing (Pin 31)
VIH
CLK_IN ^VIL
LV24100LP
tCH
tCL
Symbol
tCH
tCL
fext
VIH
VIL
Conditions
Clock High-level time
Clock Low-level time
External clock frequency
High level input voltage level
Low level input voltage level
min
36
36
32
0.7VDD
0
Ratings
typ
-
-
-
-
-
Unit
max
15625
ns
15625
ns
14000
kHz
VDD
V
0.6
V
Digital Interface
• 3-wire bus (For communication line)
Access to the LV24100 is done through the 3-wire bus.
CLOCK
Data strobe, input to the LV24100
NR_W
Command (Read or write data), input to the LV24100
DATA
Bi-directional pin:
Written data in to the LV24100 when NR_W is high,
Read data from the LV24100 when NR_W is low.
The LV24100 can be configured to generate interrupt through the DATA-line. When interrupt mode is selected, care
should be taken that the DATA-line connection to the application micro-controller also supports interrupt.
When the required timing window for frequency measurements is not generated by the application micro-controller, an
external clock must be connected to CLK_IN pin of the LV24100.
• Register map
The LV24100 registers are divided in 3 blocks:
Block 01h
Status and measurement
Block 02h
FM Control
Block 03h
AM control
To access a register in a block, the block must be first selected by writing the block number to the BLK_SEL register.
Block selection can be skipped for subsequent accesses to other registers in the same block.
No.A0194-8/18