LV24100LP Datasheet, PDF (15/18 Pages) Sanyo Semicon Device – Bi-CMOS IC FM and AM Tuner IC for Small Portable Equipment

LV24100LP
Block 2, Register 08h-STEREO_CTRL-Stereo Control Register(Write-only)
7
6
5
4
3
FRCST
FMCS[2:0]
DLT_TNE
Bit 7:
Bit 6-4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
FRCST: Force stereo bit
0 = Normal mode
1 = Force stereo mode for test
FMCS[2:0]: FM channel separation bits
0…7=FM channel separation level
DLT_TNE: Delta tune bit
0 = Decrease delta tune
1 = Normal delta tune
PILOTCANC: Pilot cancellation bit
0 = No pilot cancellation
1 = Pilot cancellation enabled
SD_PM: Stereo decoder PLL mute bit
0 = Stereo decoder PLL not muted(normal operation)
1 = Stereo decoder PLL is muted(presetting mode)
ST_M: FM stereo/mono mode bit
0 = Stereo mode
1 = Mono mode
2
PILOTCANC
Block 2, Register 09h-AUDIO_CTRL1-Audio Control 1 Register(Write-only)
7
6
5
4
3
2
Reserved
Bit 7-1:
Bit 0:
Reserved: should be written with 0
nAUBST: Audio output level boost bit
0 = Boost output level with 3dB
1 = No output level boosting
Block 2, Register 0Ah-AUDIO_CTRL2-Audio Control 2 Register(Write-only)
7
6
5
4
3
2
Reserved
DEEMP
Reserved
Bit 7-6:
Bit 5:
Bit 4-0:
Reserved: should be written with 1
DEEMP: De-emphasis bit
0 = De-emphasis 50μs.
1 = De-emphasis 75μs.
Reserved: should be written with 0
Block 2, Register 0Bh-PW_SCTRL-Power and Soft Control Register(Write-only)
7
6
5
4
3
2
SS_CTRL
SM_CTRL
Bit 7-5:
SS_CTRL: Soft stereo control bits(8 levels)
000b = Minimal soft stereo(off)
111b = Maximal soft stereo level
Bit 4-2:
SM_CTRL: Soft audio mute bits(8 levels)
000b = Minimal soft audio mute(off)
111b = Maximal soft audio mute level
Bit 1:
Reserved: should be written with 0
Bit 0:
PW_RAD: Radio circuitry power bit
0 = Radio circuitry is switched OFF.
1 = Switch radio circuitry ON
Note: PW_RAD is 0 at power up
Block 3, Register 02h-AM_ACAP-AM Antenna Capacitor Bank Register(Write-only)
7
6
5
4
3
2
AMCAP[7:0]
Bit 7-0:
AMCAP[7:0]: CAP bank value to control the AM antenna frequency
Note: AM antenna capacitor bank is controlled by 10 bits. The upper 2 bits are located in AM_FE register.
Negative control: de frequency decreases when increasing the register’s value.
1
SD_PM
1
1
1
Reserved
1
0
ST_M
0
nAUBST
0
0
PW_RAD
0
No.A0194-15/18