LC75817E Datasheet, PDF (4/43 Pages) Sanyo Semicon Device – 1/8 to 1/10 Duty Dot Matrix LCD Display Controller/Driver with Key Input Function

LC75817E, 75817W
Specifications
Absolute Maximum Ratings at Ta = 25°C, V_SS = 0 V
Parameter
Maximum supply voltage
Input voltage
Output voltage
Output current
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
V_DD max
V_LCD max
V_IN1
V_IN2
V_IN3
V_OUT1
V_OUT2
V_OUT3
I_OUT1
I_OUT2
I_OUT3
I_OUT4
Pd max
Topr
Tstg
Conditions
V_DD
V_LCD
CE, CL, DI, INH
OSCI, KI1 to KI5, TEST
V_LCD1, V_LCD2, V_LCD3, V_LCD4
DO
OSCO, KS1 to KS6, P1 to P4
V_LCD0, S1 to S60, COM1 to COM10
S1 to S60
COM1 to COM10
KS1 to KS6
P1 to P4
Ta = 85°C
Ratings
Unit
–0.3 to +7.0
V
–0.3 to +11.0
V
–0.3 to +7.0
V
–0.3 to V_DD + 0.3
V
–0.3 to V_LCD + 0.3
V
–0.3 to +7.0
V
–0.3 to V_DD + 0.3
V
–0.3 to V_LCD + 0.3
V
300
µA
3
mA
1
mA
5
mA
200
mW
–40 to +85
°C
–55 to +125
°C
Allowable Operating Ranges at Ta = –40 to +85°C, V_SS = 0 V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V_DD
V_DD
4.5
When the display contrast adjustment circuit is used.
7.0
V_LCD
When the display contrast adjustment circuit is not used.
4.5
6.0
V
10.0
V
10.0
V
Output voltage
Input voltage
Input high level voltage
Input low level voltage
Recommended external resistance
Recommended external capacitance
Guaranteed oscillation range
Data setup time
Data hold time
CE wait time
CE setup time
CE hold time
High level clock pulse width
V_LCD0
V_LCD1
V_LCD2
V_LCD3
V_LCD4
V_IH1
V_IH2
V_IH3
V_IL1
V_IL2
R_OSC
C_OSC
f_OSC
t_ds
t_dh
t_cp
t_cs
t_ch
tøH
V_LCD0
V_LCD1
V_LCD2
V_LCD3
V_LCD4
CE, CL, DI, INH
OSCI
KI1 to KI5
CE, CL, DI, INH, KI1 to KI5
OSCI
OSCI, OSCO
OSCI, OSCO
OSC
CL, DI: Figure 2
CL, DI: Figure 2
CE, CL: Figure 2
CE, CL: Figure 2
CE, CL: Figure 2
CL: Figure 2
V_LCD4+4.5
V_LCD
V
3/4 (V_LCD0_–V_LCD4) V_LCD0
V
2/4 (V_LCD0_–V_LCD4) V_LCD0
V
1/4 (V_LCD0_–V_LCD4) V_LCD0
V
0
1.5
V
0.8 V_DD
0.7 V_DD
0.6 V_DD
0
0
6.0
V
V_DD
V
V_DD
V
0.2 V_DD
V
0.3 V_DD
V
33
kΩ
220
pF
150
300
600 kHz
160
ns
160
ns
160
ns
160
ns
160
ns
160
ns
Low level clock pulse width
tøL
CL: Figure 2
160
ns
DO output delay time
DO rise time
t_dc
DO, R_PU = 4.7kΩ, C_L = 10pF: Figure 2*¹
t_dr
DO, R_PU = 4.7kΩ, C_L = 10pF: Figure 2*¹
1.5
µs
1.5
µs
Note: *1. Since the DO pin is an open-drain output, these times depend on the values of the pull-up resistor R_PU and the load capacitance C_L.
No. 6144-4/43