LC878496PB Datasheet, PDF (15/29 Pages) Sanyo Semicon Device – 8-bit ETR Microcontroller

LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB
Continued from preceding page.
Parameter
HALT mode
consumption
current
(Note 7-1)
Symbol
Pins/
Remarks
Conditions
VDD[V]
min
IDDHALT(1)
IDDHALT(2)
VDD1
=VDD2
=VDD3
=VDD4
• HALT mode
• FmCF=13.5MHz oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 13.5MHz side
• Internal RC oscillation stopped
• Frequency variable RC oscillation stopped
4.5 to 5.5
3.0 to 4.5
• 1/1 frequency division ratio.
Specification
typ
max
unit
2.0
3.0
1.8
2.5
IDDHALT(3)
IDDHALT(4)
IDDHALT(5)
IDDHALT(6)
• HALT mode
• FmCF=8MHz oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 8MHz side
• Internal RC oscillation stopped
• Frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
• HALT mode
• FmCF=4MHz oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 4MHz side
• Internal RC oscillation stopped
• Frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
4.5 to 5.5
3.0 to 4.5
4.5 to 5.5
3.0 to 4.5
1.2
1.8
1.0
1.5
0.6
0.9
mA
0.5
0.7
IDDHALT(7)
IDDHALT(8)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to internal RC oscillation
• Frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
4.5 to 5.5
3.0 to 4.5
0.5
1.0
0.3
0.8
IDDHALT(9)
IDDHALT(10)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX'al=32.768kHz by crystal oscillation
mode.
• Internal RC oscillation stopped
• System clock set to 1MHz with frequency
variable RC oscillation
• 1/2 frequency division ratio.
4.5 to 5.5
3.0 to 4.5
1.0
2.0
0.8
1.5
IDDHALT(11)
IDDHALT(12)
Current drain
during HOLD
mode
IDDHOLD(1)
IDDHOLD(2)
VDD1
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX'al=32.768kHz by crystal oscillation
mode.
• System clock set to 32.768kHz side.
• Internal RC oscillation stopped
• Frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
• HOLD mode
4.5 to 5.5
3.0 to 4.5
4.5 to 5.5
3.0 to 4.5
250
500
200
400
μA
1.5
20.0
1.0
18.0
Current drain
during time-
base clock
HOLD mode
IDDHOLD(3) VDD1
IDDHOLD(4)
• Timer HOLD mode
• FmX'tal=32.768kHz by crystal oscillation
mode
4.5 to 5.5
3.0 to 4.5
150
300
100
200
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
General-purpose I/O port "L" output when the above-mentioned data is measured
However, the P0 port is an input setting because of the mode setting
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No.A1795-15/29