K4S643232F Datasheet, PDF (9/12 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232F
CMOS SDRAM
Parameter
Symbol
Row active to row active delay tRRD(min)
RAS to CAS delay
tRCD(min)
Row precharge time
tRP(min)
Row active time
tRAS(min)
tRAS(max)
Row cycle time
tRC(min)
-45
9
18
18
40.5
58.5
Version
-50
-55
-60
10
11
12
15
16.5
18
15
16.5
18
40
38.5
42
100
55
55
60
Unit
-70
14
ns
20
ns
20
ns
49
ns
us
70
ns
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
CLK cycle time
CAS Latency=3
CAS Latency=2
CLK to valid
output delay
CAS Latency=3
CAS Latency=2
Output data hold time
CLK high pulse
width
CAS Latency=3
CAS Latency=2
CLK low
pulse width
CAS Latency=3
CAS Latency=2
Input setup time
CAS Latency=3
CAS Latency=2
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
CAS latency=3
CAS latency=2
Symbol
tCC
tSAC
tOH
tCH
tCL
tSS
tSH
tSLZ
tSHZ
-45
Min Max
4.5
1000
10
- 4.0
-
6
2
-
1.75 -
3
-
1.75 -
3
-
1.2 -
2.5 -
1
-
1
-
- 4.0
-
6
-50
Min Max
5
1000
10
- 4.5
-
6
2
-
2
-
3
-
2
-
3
-
1.5 -
2.5 -
1
-
1
-
- 4.5
-
6
-55
Min Max
5.5
1000
10
- 5.0
-
6
2
-
2
-
3
-
2
-
3
-
1.5 -
2.5 -
1
-
1
-
- 5.0
-
6
-60
Min Max
6
1000
10
- 5.5
-
6
2
-
2.5 -
3
-
2.5 -
3
-
1.5 -
2.5 -
1
-
1
-
- 5.5
-
6
-70
Unit Note
Min Max
7
1000 ns 1
10
- 5.5
ns 1, 2
-
6
2
- ns 2
3
-
ns 3
3
-
3
-
ns 3
3
-
1.75 -
2.5 -
ns 3
1
- ns 3
1
- ns 2
- 5.5
ns -
-
6
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 1.0 (Jan. 2002)
-9-