K4S643232F Datasheet, PDF (3/12 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232F
CMOS SDRAM
512K x 32Bit x 4 Banks Synchronous DRAM
FEATURES
• 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency ( 2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 15.6us refresh duty cycle
GENERAL DESCRIPTION
The K4S643232F is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNG′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
ORDERING INFORMATION
Part NO.
Max Freq.
K4S643232F-TC/L45
222MHz
K4S643232F-TC/L50
200MHz
K4S643232F-TC/L55
183MHz
K4S643232F-TC/L60
166MHz
K4S643232F-TC/L70
143MHz
Interface Package
LVTTL
86
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
Data Input Register
Bank Select
CLK
ADD
LCKE
LRAS LCBR
LWE
LCAS
512K x 32
512K x 32
512K x 32
512K x 32
Column Decoder
Latency & Burst Length
Programming Register
LWCBR
Timing Register
LWE
LDQM
DQi
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to
change products or specification without
notice.
Rev. 1.0 (Jan. 2002)
-3-