K4S643232F Datasheet, PDF (8/12 Pages) Samsung semiconductor – 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

K4S643232F
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
Value
AC input levels (Vih/Vil)
2.4/0.4
Input timing measurement reference level
1.4
Input rise and fall time
tr/tf = 1/1
Output timing measurement reference level
1.4
Output load condition
See Fig. 2
3.3V
Output
870Ω
1200Ω
30pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
CMOS SDRAM
Unit
V
V
ns
V
Z0 = 50Ω
Vtt = 1.4V
50Ω
30pF
(Fig. 1) DC output load circuit
Notes : 1. The VDD condition of K4S643232F-45/50/55/60 is 3.135V ~ 3.6V
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
CAS Latency
CL
CLK cycle time
tCC(min)
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
Row precharge time
tRP(min)
Row active time
tRAS(min)
tRAS(max)
Row cycle time
tRC(min)
Last data in to row precharge
tRDL(min)
Last data in to new col.address delay tCDL(min)
Last data in to burst stop
Col. address to col. address delay
tBDL(min)
tCCD(min)
Mode Register Set cycle time
tMRS(min)
Number of valid
output data
CAS Latency=3
CAS Latency=2
-45
3
2
4.5 10
4
2
4
2
9
5
13 7
-50
3
2
5 10
3
2
3
2
8
5
11 7
(Fig. 2) AC output load circuit
Version
-55
3
2
5.5 10
2
3
2
3
2
7
5
100
10 7
2
1
1
1
2
2
1
-60
3
2
6 10
3
2
3
2
7
5
10 7
-70
3
2
7 10
3
2
3
2
7
5
10 7
Unit Note
CLK
ns
CLK 1
CLK 1
CLK 1
CLK 1
us
CLK 1
CLK 2
CLK 2
CLK 2
CLK 3
CLK
ea 4
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following ns-unit based AC table.
Rev. 1.0 (Jan. 2002)
-8-