K1S3216B1C Datasheet, PDF (9/10 Pages) Samsung semiconductor – 2Mx16 bit Uni-Transistor Random Access Memory

K1S3216B1C
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
CS1
CS2
tAS(3)
tCW(2)
tAW
UB, LB
WE
tBW
tWP(1)
Data in
tWR(4)
tDW
tDH
Data Valid
Preliminary
UtRAM
Data out
High-Z
High-Z
TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)
tWC
Address
CS1
CS2
tCW(2)
tAW
UB, LB
WE
tAS(3)
tBW
tWP(1)
Data in
tWR(4)
tDW
tDH
Data Valid
Data out
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.
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Revision 0.1
June 2003