K1S3216B1C Datasheet, PDF (7/10 Pages) Samsung semiconductor – 2Mx16 bit Uni-Transistor Random Access Memory

K1S3216B1C
Preliminary
UtRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)
Address
Data Out
tRC
tAA
tOH
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Address
CS1
tRC
tAA
tOH
tCO
CS2
UB, LB
OE
Data out
High-Z
tBA
tOE
tOLZ
tBLZ
tLZ
Data Valid
tHZ
tBHZ
tOHZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
3. tOE(max) is met only when OE becomes enabled after tAA(max).
4. If invalid address signals shorter than min. tRC are continuously repeated for over 4us, the device needs a normal read timing(tRC) or
needs to sustain standby state for min. tRC at least once in every 4us.
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Revision 0.1
June 2003