K9F1208Q0A Datasheet, PDF (8/39 Pages) Samsung semiconductor – 512Mb/256Mb 1.8V NAND Flash Errata

K9F5608U0C-VCB0,VIB0,FCB0,FIB0
K9F5608Q0C-DCB0,DIB0,HCB0,HIB0
K9F5608U0C-YCB0,YIB0,PCB0,PIB0
K9F5608U0C-DCB0,DIB0,HCB0,HIB0
K9F5616Q0C-DCB0,DIB0,HCB0,HIB0
K9F5616U0C-YCB0,YIB0,PCB0,PIB0
K9F5616U0C-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
Figure 1-1. K9F5608X0C (X8) FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
A9 - A24
A0 - A7
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
256M + 8M Bit
NAND Flash
ARRAY
(512 + 16)Byte x 65536
Command
A8
Command
Register
Page Register & S/A
Y-Gating
I/O Buffers & Latches
CE
Control Logic
RE
& High Voltage
WE
Generator
Global Buffers
Output
Driver
VCC/VCCQ
VSS
I/0 0
I/0 7
CLE ALE WP
Figure 2-1. K9F5608X0C (X8) ARRAY ORGANIZATION
1 Block =32 Pages
= (16K + 512) Byte
64K Pages
(=2,048 Blocks)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
512Byte
16 Byte
1 Page = 528 Byte
1 Block = 528 Byte x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 2048 Blocks
= 264 Mbits
8 bit
Page Register
512 Byte
16 Byte
I/O 0 ~ I/O 7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
1st Cycle
A0
A1
A2
A3
A4
A5
A6
2nd Cycle A9
A10
A11
A12
A13
A14
A15
3rd Cycle A17
A18
A19
A20
A21
A22
A23
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* The device ignores any additional input of address cycles than reguired.
I/O 7
A7
A16
A24
Column Address
Row Address
(Page Address)
7