K4S511632D Datasheet, PDF (8/9 Pages) Samsung semiconductor – DDP 512Mbit SDRAM 8M x 16bit x 4 Banks Synchronous DRAM LVTTL

K4S511632D
CMOS SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
-7C
Min Max
-75
Min Max
-1H
Min Max
CAS latency=3
CLK cycle time
tCC
CAS latency=2
7.5
7.5
10
1000
1000
1000
7.5
10
10
CLK to valid
CAS latency=3
5.4
5.4
6
tSAC
output delay
CAS latency=2
5.4
6
6
Output data
CAS latency=3
3
3
3
hold time
tO H
CAS latency=2
3
3
3
CLK high pulse width
tCH
2.5
2.5
3
CLK low pulse width
tCL
2.5
2.5
3
Input setup time
tSS
1.5
1.5
2
Input hold time
tSH
0.8
0.8
1
CLK to output in Low-Z
tSLZ
1
1
1
CLK to output
CAS latency=3
5.4
5.4
6
in Hi-Z
CAS latency=2
tSHZ
5.4
6
6
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
-1L
Min Max
10
1000
12
6
7
3
3
3
3
2
1
1
6
7
Unit Note
ns 1
ns 1,2
ns 2
ns 3
ns 3
ns 3
ns 3
ns 2
ns
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Output rise time
Symbol
Condition
Min
Typ
trh
Measure in linear
1.37
region : 1.2V ~1.8V
Max
4.37
Output fall time
tfh
Measure in linear
1.30
3.8
region : 1.2V ~1.8V
Output rise time
trh
Measure in linear
2.8
3.9
5.6
region : 1.2V ~1.8V
Output fall time
tfh
Measure in linear
2.0
2.9
5.0
region : 1.2V ~1.8V
Notes : 1. Rise time specification based on 0pF + 50 Ohms to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 Ohms to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
Unit
Volts/ns
Volts/ns
Volts/ns
Volts/ns
Notes
3
3
1,2
1,2
Rev. 0.0 July. 2002