K4S511632D Datasheet, PDF (6/9 Pages) Samsung semiconductor – DDP 512Mbit SDRAM 8M x 16bit x 4 Banks Synchronous DRAM LVTTL

K4S511632D
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Operating current
(One bank active)
Symbol
Test Condition
ICC1
Burst length = 1
tR C ≥ tRC(min)
IO = 0 mA
Version
Unit Note
-7C -75 -1H -1L
200 180 180 180 mA
1
Precharge standby current in
power-down mode
IC C 2P
ICC2PS
CKE ≤ V IL(max), tCC = 10ns
CKE & CLK ≤ V IL(max), tCC = ∞
4
mA
4
CKE ≥ V I H(min), CS ≥ VI H(min), tCC = 10ns
ICC2N _{Input signals are changed one time during 20ns}
40
Precharge standby current in
non power-down mode
ICC2NS ^{CKE ≥ V I H(min), CLK ≤ VIL(max), tCC = ∞}
mA
20
Input signals are stable
Active Standby current
in power-down mode
IC C 3P
ICC3PS
CKE ≤ V IL(max), tCC = 10ns
CKE & CLK ≤ V IL(max), tCC = ∞
12
mA
12
Active standby current in
ICC3N
CKE ≥ V I H(min), CS ≥ VI H(min), tCC = 10ns
Input signals are changed one time during 20ns
60
mA
non power-down mode
(One bank active)
CKE ≥ V I H(min), CLK ≤ VIL(max), tCC = ∞
ICC3NS
Input signals are stable
50
mA
Operating current
(Burst mode)
Refresh current
Self refresh current
ICC4
ICC5
IO = 0 mA
Page burst
4banks activated.
tCCD = 2CLKs
tR C ≥ tRC(min)
ICC6 CKE ≤ 0.2V
220 220 240 240 mA
1
440 400 380 380 mA
2
C
6
mA
3
L
3
mA
4
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S511632D-KC**
4. K4S511632D-KL**
5. Unless otherwise noticed, input swing level is CMOS(V IH/VIL=V DDQ/V SSQ).
Rev. 0.0 July. 2002