DS_K7N803645B Datasheet, PDF (7/18 Pages) Samsung semiconductor – 256Kx36 & 512Kx18-Bit Pipelined NtRAMTM

K7N803645B
K7N801845B
256Kx36 & 512Kx18 Pipelined NtRAM^TM
STATE DIAGRAM FOR NtRAM^TM
WRITE
READ
READ ^BEGIN
READ
READ
DS
DESELECT
WRITE
DS
BEGIN _WRITE
WRITE
DS
READ
BURST ^BURST
READ
RITE
W
DS
BURST _BURST
WRITE
COMMAND
DS
READ
WRITE
BURST
DESELECT
BEGIN READ
BEGIN WRITE
BEGIN READ
BEGIN WRITE
CONTINUE DESELECT
ACTION
Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does
not change the state of the device.
2. States change on the rising edge of the clock(CLK)
-7-
Nov 2003
Rev 3.0