DS_K7N803645B Datasheet, PDF (11/18 Pages) Samsung semiconductor – 256Kx36 & 512Kx18-Bit Pipelined NtRAMTM

K7N803645B
K7N801845B
256Kx36 & 512Kx18 Pipelined NtRAM^TM
Dout
Output Load(A)
Zo=50Ω
RL=50Ω
30pF*
VL=1.25V
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
1538Ω
+2.5V
1667Ω
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(VDD=2.5V ±5%, TA=0 to 70°C)
PARAMETER
Cycle Time
Clock Access Time
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
CKE Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High (WE, BWX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
CKE Hold from Clock High
Data Hold from Clock High
Write Hold from Clock High (WE, BWEX)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
ZZ Low to Power Up
SYMBOL
tCYC
tCD
tOE
tLZC
tOH
tLZOE
tHZOE
tHZC
tCH
tCL
tAS
tCES
tDS
tWS
tADVS
tCSS
tAH
tCEH
tDH
tWH
tADVH
tCSH
tPDS
tPUS
-16
MIN
MAX
6.0
-
-
3.5
-
3.5
1.5
-
1.5
-
0
-
-
3.0
-
3.0
2.2
-
2.2
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
2
-
2
-
-13
MIN
MAX
7.5
-
-
4.2
-
4.2
1.5
-
1.5
-
0
-
-
3.5
-
3.5
3.0
-
3.0
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
0.5
-
2
-
2
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycle
cycle
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
4. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
Both cases must meet setup and hold times.
5. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC.
The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions
(0°C,2.625V) than tHZC, which is a Max. parameter(worst case at 70°C,2.375V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
- 11 -
Nov 2003
Rev 3.0