DS_K7N323601M Datasheet, PDF (7/24 Pages) Samsung semiconductor – 1Mx36 & 2Mx18-Bit Pipelined NtRAM

K7N323601M
K7N321801M
1Mx36 & 2Mx18 Pipelined NtRAM^TM
165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW)
K7N321801M(2Mx18)
1
2
3
4
5
6
7
8
9
10
A
NC
A
CS 1
BWb
NC
CS2
CKE
ADV
A
A
B
NC
A
CS2
NC
BWa
CLK
WE
OE
A
A
C
NC
NC
V DDQ
VSS
V SS
VSS
VSS
VSS
VDDQ
NC
D
NC
DQb
V DDQ
V DD
V SS
VSS
VSS
VDD
VDDQ
NC
E
NC
DQb
V DDQ
V DD
V SS
VSS
VSS
VDD
VDDQ
NC
F
NC
DQb
V DDQ
V DD
V SS
VSS
VSS
VDD
VDDQ
NC
G
NC
DQb
V DDQ
V DD
V SS
VSS
VSS
VDD
VDDQ
NC
H
NC
VDD
NC
V DD
V SS
VSS
VSS
VDD
NC
NC
J
DQb
NC
V DDQ
V DD
V SS
VSS
VSS
VDD
VDDQ
DQa
K
DQb
NC
V DDQ
V DD
V SS
VSS
VSS
VDD
VDDQ
DQa
L
DQb
NC
V DDQ
V DD
V SS
VSS
VSS
VDD
VDDQ
DQa
M
DQb
NC
V DDQ
V DD
V SS
VSS
VSS
VDD
VDDQ
DQa
N
DQPb
NC
V DDQ
VSS
NC
NC
NC
VSS
VDDQ
NC
P
NC
NC
A
A
TDI
A1*
TDO
A
A
A
R
LBO
A
A
A
TMS
A0*
TCK
A
A
A
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
11
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
NC
A
PIN NAME
SYMBOL
A
A0,A1
ADV
WE
CLK
CKE
CS1
CS2
CS2
BWx
(x=a,b)
OE
ZZ
LBO
TCK
TMS
TDI
TDO
PIN NAME
Address Inputs
Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
SYMBOL
VDD
VSS
N.C.
DQa
DQb
DQPa, Pb
VDDQ
PIN NAME
Power Supply
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Output Power Supply
-7-
Nov. 2003
Rev 2.0