DS_K7N323601M Datasheet, PDF (5/24 Pages) Samsung semiconductor – 1Mx36 & 2Mx18-Bit Pipelined NtRAM

K7N323601M
K7N321801M
PIN CONFIGURATION(TOP VIEW)
1Mx36 & 2Mx18 Pipelined NtRAM^TM
N.C.
1
N.C.
2
N.C.
3
VDDQ
4
VSSQ
5
N.C.
6
N.C.
7
DQb8
8
DQb7
9
VSSQ
10
VDDQ
11
DQb6
12
DQb5
13
VDD
14
VDD
15
VDD
16
VSS
17
DQb4
18
DQb3
19
VDDQ
20
VSSQ
21
DQb2
22
DQb1
23
DQb0
24
N.C.
25
VSSQ
26
VDDQ
27
N.C.
28
N.C.
29
N.C.
30
100 Pin TQFP
(20mm x 14mm)
K7N321801M(2Mx18)
80
A10
79
N.C.
78
N.C.
77
VDDQ
76
VSSQ
75
N.C.
74
DQa0
73
DQa1
72
DQa2
71
VSSQ
70
VDDQ
69
DQa3
68
DQa4
67
VSS
66
VDD
65
VDD
64
ZZ
63
DQa5
62
DQa6
61
VDDQ
60
VSSQ
59
DQa7
58
DQa8
57
N.C.
56
N.C.
55
VSSQ
54
VDDQ
53
N.C.
52
N.C.
51
N.C.
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A20
Address Inputs
ADV
Address Advance/Load
WE
Read/Write Control Input
CLK
Clock
CKE
Clock Enable
CS1
Chip Select
CS2
Chip Select
CS2
Chip Select
BW x(x=a,b) Byte Write Inputs
OE
Output Enable
ZZ
Power Sleep Mode
LBO
Burst Mode Control
32,33,34,35,36,37,43
44,45,46,47,48,49,50,
80,81,82,83,84,99,100
85
88
89
87
98
97
92
93,94
86
64
31
VDD
VSS
N.C.
DQa0~a 8
DQb0~b 8
VDDQ
VSSQ
Power Supply(+3.3V) 14,15,16,41,65,66,91
Ground
17,40,67,90
No Connect
1,2,3,6,7,25,28,29,30,
38,39,42,51,52,53,
56,57,75,78,79,95,96
Data Inputs/Outputs 58,59,62,63,68,69,72,73,74
Data Inputs/Outputs 8,9,12,13,18,19,22,23,24
Output Power Supply 4,11,20,27,54,61,70,77
(3.3V or 2.5V)
Output Ground
5,10,21,26,55,60,71,76
NOTE : A 0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-5-
Nov. 2003
Rev 2.0