M374S6453CTS Datasheet, PDF (6/11 Pages) Samsung semiconductor – M374S6453CTS PC133/PC100 Unbuffered SDRAM DIMM

M374S6453CTS
PC133/PC100 Unbuffered DIMM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
Value
Unit
AC input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
Output
870Ω
1200Ω
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Z0 = 50Ω
50Ω
50pF
(Fig. 1) DC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
(Fig. 2) AC output load circuit
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Symbol
-7C
tRRD(min)
15
tRCD(min)
15
tRP(min)
15
tRAS(min)
45
tRAS(max)
tRC(min)
60
tRDL(min)
tDAL(min)
Version
-7A
-1H
15
20
20
20
20
20
45
50
100
65
70
2
2 CLK + tRP
Unit
Note
-1L
20
ns
1
20
ns
1
20
ns
1
50
ns
1
us
70
ns
1
CLK
2, 5
-
5
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
Number of valid output data
CAS latency=3
2
ea
4
CAS latency=2
1
Notes : _{1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time}
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
REV. 0.1 Sept. 2001